2006年08月26日

SPARTAN-3E³«È¯ºÇ½é¤Î°ìÊâ

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¤Ç¡¢Ä´ºº¤·¤¿¤È¤³¤í¡¢FPGA¤Ç¤ä¤ë¾ì¹ç¤Ï¡¢¡ÖLCD¥³¥ó¥È¥í¡¼¥é¡×¤ò½ñ¤¯É¬Íפ¬¤¢¤ë¤è¤¦¤Ç¡¢¡Öʸ»ú¤Îɽ¼¨¡×¤ÎÆñÅ٤Ϲ⤤¤è¤¦¤Ç¤¹¡£
¤½¤³¤Ç¡¢¡ÖLED¤ò¸÷¤é¤»¤ë¡×¤È¤¤¤¦¥×¥í¥°¥é¥à¤ò½ñ¤¤¤Æ¤ß¤è¤¦¤«¤È»×¤¤¤Þ¤¹¡£¤³¤ì¤¬¡¢°ìÈÖ¤ÎÆþÌç¥×¥í¥°¥é¥à¤é¤·¤¤¤Î¤Ç¡£
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1¡¤¿·µ¬¥×¥í¥¸¥§¥¯¥ÈºîÀ®
¤Þ¤º¡¢ISE¤òµ¯Æ°¤·¤Æ¤¯¤À¤µ¤¤¡£
¤½¤·¤Æ¡¢µ¯Æ°¸å¡¢[File] ¢ª [New Project] ¤È¥¯¥ê¥Ã¥¯¤·¤Þ¤¹¡£

1-1¡¤[Create New Project]¥¦¥£¥ó¥É¥¦
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Project Name
Project Location
Top-Level Source Type:HDL


1-2¡¤[Device Properties]¥¦¥£¥ó¥É¥¦
¥Ç¥Ð¥¤¥¹¤ÎÀßÄê¾ðÊó¤òÀßÄꤷ¤Þ¤¹¡£Spartan-3E¤Ç¤Ï¡¢²¼µ­¤Î¤è¤¦¤ÊÃͤòÆþÎϤ·¤Þ¤¹¡£

Product Category:ALL
Family:spartan3e
Device:xc3s500e
Package:fg320
Speed:-4
Top-Level Source Type:HDL
Synthesis Tool:XST(VHDL/Verilog)
Simulator:ISE Simulator(VHDL/Verilog)
Enable Enhanced Design Summary:¥Á¥§¥Ã¥¯

1-3¡¤[Select Source Type]¥¦¥£¥ó¥É¥¦
¥½¡¼¥¹¥Õ¥¡¥¤¥ë¤òºîÀ®¤·¤Þ¤¹¡£¥Õ¥¡¥¤¥ë̾¤Ï¡¢¤ª¹¥¤­¤Ê¤â¤Î¤Ç¹½¤¤¤Þ¤»¤ó¡£

Verilog Module¤òÁªÂò
File name:sw_led

1-4¡¤[Define Module]¥¦¥£¥ó¥É¥¦
¥Ý¡¼¥È¤ÎÆþ½ÐÎÏÀßÄê¤ò¤·¤Þ¤¹¡£²¼µ­¤Î¤è¤¦¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£

¡¦°ì¹ÔÌÜ
Port Name:led
Direction:output
¡¦Æó¹ÔÌÜ
Port Name:sw
Direction:input


1-5¡¤[Add Existing Sources]¥¦¥£¥ó¥É¥¦
Äɲ彡¼¥¹¤¬¤¢¤ì¤Ð¡¢»ØÄꤷ¤Þ¤¹¤¬¡¢º£²ó¤Ï¥Ê¥·¤ÇOK¤Ç¤¹¡£


1-6¡¤½ªÎ»
[Finish]¤ò¥¯¥ê¥Ã¥¯¤·¤Þ¤¹¡£
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¤Ä¤Å¤¤¤Æ¡¢¥×¥í¥°¥é¥ß¥ó¥°¤ò¹Ô¤¤¤Þ¤¹¡£


2¡¤¥×¥í¥°¥é¥àºîÀ®
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assign led1 = sw;

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¤Ä¤Å¤¤¤Æ¡¢ÇÛÀþ¤ò¹Ô¤¤¤Þ¤¹¡£¤É¤¦¤ä¤é¡¢FPGA¤Ç¤Î¥­¥â¤È¤Ê¤ëÉôʬ¤Î¤è¤¦¤Ç¤¹¡£


3¡¤ÇÛÀþ¥Õ¥¡¥¤¥ë¤ÎºîÀ®
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3-1¡¤[Select Source Type]¥¦¥£¥ó¥É¥¦
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[Select Source Type]¥¦¥£¥ó¥É¥¦¤¬¡¢½Ð¸½¤·¤Þ¤¹¤Î¤Ç¡¢²¼µ­¤Î¤è¤¦¤Ë¤·¤Þ¤¹¡£

Implementation Constraints File¤òÁªÂò
File name:sw_led


3-2¡¤[Associate Source]¥¦¥£¥ó¥É¥¦
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¤½¤¦¤¹¤ë¤È¡¢[Sources]¥¦¥£¥ó¥É¥¦ ¤Ë¡¢ucf¥Õ¥¡¥¤¥ë¤¬Äɲ䵤ì¤Þ¤¹¡£


3-3¡¤[Xilinx PACE]¥¦¥£¥ó¥É¥¦
¾åµ­¤ÇºîÀ®¤·¤¿ucf¥Õ¥¡¥¤¥ë¤òÁªÂò¤¹¤ë¤È¡¢º¸²¼¤Î[Processes]¥¦¥£¥ó¥É¥¦¤ÎÆâÍƤ¬ÊѤï¤ê¤Þ¤¹¡£
¤½¤ÎÃæ¤Î [User Constraints] ¢ª [Assign Package Pins]¤ò¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤·¤Þ¤¹¡£

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3-3-1¡¤[Design Object List]¥¦¥£¥ó¥É¥¦
[Design Object List]¥¦¥£¥ó¥É¥¦¤Ë¡¢¡Ö1-4¡¤[[Define Module]¡×¤Ç»ØÄꤷ¤¿¥Ç¥Ð¥¤¥¹¤¬¤¢¤ë¤Ï¤º¤Ç¤¹¡£
¤½¤³¤Î[Loc] ¤Ë¡¢²¼µ­¤Î¤è¤¦¤ËÆþÎϤ·¤Þ¤¹¡£

led1 = F12
sw = L13


3-3-2¡¤[Save]¤¹¤ë
[File] ¢ª [Save]¤Ç¡¢¥»¡¼¥Ö¤ò¹Ô¤¤¤Þ¤¹¡£
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[Symplify Verilog Default:[]]

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4-1¡¤[Generate Programming File]¥¦¥£¥ó¥É¥¦
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[Process Properties] ¥¦¥£¥ó¥É¥¦¤¬½Ð¸½¤·¤Þ¤¹¤Î¤Ç¡¢²¼µ­¤Î¤è¤¦¤Ë¤·¡¢[OK]¤ò¥¯¥ê¥Ã¥¯¤·¤Þ¤¹¡£

[Readback Oprions]Æâ¤Î
[Create ReadBack Data Files] ¥Á¥§¥Ã¥¯
[Create Mask File] ¥Á¥§¥Ã¥¯


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[Configure devices using Boundary-Scan]
Automatically connect to a cable and idenify Boundary-Scan chain

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4-6¡¤[Programming Properties]¥¦¥£¥ó¥É¥¦
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[Programming Properties]¥¦¥£¥ó¥É¥¦¤¬½Ð¸½¤·¤¿¤é¡¢²¿¤âÊѹ¹¤»¤º¤Ë¡¢[OK]¤ò¥¯¥ê¥Ã¥¯¤·¤Þ¤¹¡£

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